This section contains a brief description of the LEON3 SPARC V8 processor implementation developed by Gaisler Research, with an emphasis on information. LEON3 is a synthesizable VHDL model of a bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly. LEON3 Processor. SPARC V8 instruction set with V8e extensions; Advanced 7- stage pipeline; Hardware multiply, divide and MAC units; High-performance, fully .

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This page presents the major microprocessors used or to be used in most European space applications. It is highly configurable, and was designed for embedded applications with the following features on-chip:.

The certification was completed on May 1, This allows new users to quickly define a suitable custom configuration. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. It features the following:.

Hardware iCE Stratix Virtex. The NGMP has the following on-chip functions:. This page was last edited on 23 Decemberat Only netlist distribution is possible. BCC includes a small run-time with interrupt support and Pthreads library.

LEON3 32-bit processor core

Debugging is generally done using the gdb debugger, and a graphical oeon3 such as DDD or Eclipse. The model is highly configurable, and particularly suitable for system-on-a-chip SoC designs. Another objective was to loen3 able to manufacture in a Single event upset SEU tolerant sensitive semiconductor process. Currently 5 out of 5 Stars.


More information regarding these models can is available on the Aeroflex Gaisler website. A single processoe tool-chain is provided which is capable of compiling the kernel and applications for any configuration.

For industrial and high-rel applications, ports for VxWorks 5. This section and the subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution. November Learn how and when to remove this template message.

LEON3 Processor – MechatronicsUSP

Microprocessors are a core component of modern electronics and on-board computers do not escape this rule. Retrieved from ” http: Aeroflex Gaisler – Device: The LEON3 processor has the following features:.

Pre-synthesized FPGA programming files are also provided. Your rating has been changed, thanks for rating! Up to 16 CPU can be used in a multiprocessing configuration.

This article is about the family of peon3. Please improve this by adding secondary or tertiary sources.

The LEON4 processor has the following features: LEON has a dual license model: Processod prediction, 1-cycle load latency and a 32×32 multiplier results in a performance of 1. It features the following: The model is highly configurable, and particularly suitable for system-on-a-chip SoC designs.

Archived from the original PDF on This article relies too much on references to primary sources. The LEON4 processor has the following features:.

LEON3 Processor | eASIC Corporation

While the LEON2 -FT design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.


The fault-tolerance is provided at design VHDL level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware.

You have already rated this page, you can only rate it once! Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education.

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Archived copy as title Webarchive template wayback links Articles lacking reliable references from November All articles lacking reliable references Articles containing Spanish-language text Articles with Curlie links. By using this site, you agree to the Terms of Use and Privacy Policy. It is thus possible to instantiate several processor cores in the same design with different configurations. Flip-flops are protected by triple modular redundancy and all internal and external memories are protected by EDAC or parity bits.

It is highly configurable, and was designed for embedded applications with the following features on-chip: Processorr Defense and Space.